G 114
CAP. 60]
Import and Export (Strategic Commodities) Regulations
[1988 Ed.
[Subsidiary]
'fixed point processing data rate' (Rx)
The sum of
(1) 0.85 times the 'number of bits in a fixed point addition instruction' (niax); (2) 0.15 times the "number of bits in a fixed point multiplication instruction" (nimx); and
(3) 0.55 times the 'number of bits in a fixed point operand' (nox);
divided by the sum of:
(1) 0.85 times the 'execution time' for a fixed point addition (tax); and
(2) 0.15 times the 'execution time' for a fixed point multiplication (tmx) or for the fastest available subroutine (sub) to simulate a fixed point multiplication instruction if no fixed point multiplication instructions are implemented.
Thus:
Rx = [(0.85)niax + (0.15)nimx + (0.55)nox] / [(0.85)tax + (0.15)tmx]
or if no fixed point multiplication instructions are implemented (tmx = tmsub) then:
Rx = [(0.85)niax + (0.15)nimx + (0.55)nox] / [(0.85)tax + (0.15)tmsub]
NB:
If a "digital computer" has neither fixed point addition nor fixed point multiplication instructions, then its 'fixed point processing data rate' is equal to zero.
'number of bits in a:
Thus:
Fixed point addition instruction' (niax) = niax
Fixed point multiplication instruction' (nimx)
Floating point addition instruction' (niaf)
Floating point multiplication instruction' (nimf)
The appropriate shortest/single fixed or floating point instruction length which permits full direct addressing of the "main storage".
NB:
1.
When multiple instructions are required to simulate an appropriate single instruction, the number of bits in the above instructions is defined as 16 bits plus the number of bits (biax; bimx; biaf; bimf) which permits full direct addressing of the "main storage".
niax = 16 + biax
nimx = 16 + bimx
niaf = 16 + biaf
nimf = 16 + bimf
2.
If the addressing capability of an instruction is expanded by using a base register, then the "number of bits in an instruction, fixed or floating point, addition or multiplication' is the number of bits in the instruction with the standard address length including the number of bits necessary to use the base register.
'number of bits in a fixed point operand' (nox)
(a) The shortest fixed point operand length; or (b) 16 bit;
whichever is greater.
'number of bits in a floating point operand' (nof)
(a) The shortest floating point operand length; or (b) 30 bit;
whichever is greater.
G 114
CAP. 60]
Import and Export (Strategic Commodities) Regulations
[1988 Ed.
[Subsidiary]
'fixed point processing data rate' (R,)
The sum of
(1) 0.85 times the 'number of bits in a fixed point additión instruction' (njax); (2) 0.15 times the "number of bits in a fixed point multiplication instruction"
(nimx); and
(3) 0.55 times the 'number of bits in a fixed point operand' (nox);
divided by the sum of:
(1) 0.85 times the 'execution time' for a fixed point addition (†); and
(2) 0.15 times the execution time' for a fixed point multiplication (tm) or for the fastest available subroutine (sub) to simulate a fixed point multiplication instruction if no fixed point multiplication instructions are implemented.
Thus:
Rx
(0.85)njax+(0.15)nimx +(0.55)nox (0.85)tax+(0.15)x
or if no fixed point multiplication instructions are implemented (tmx
(0.85)¤;ax+(0.15)+(0.55)nox
'msub) then:
Rx
NB:
(0.85)x+(0.15)msub
If a "digital computer" has neither fixed point addition nor fixed point multiplication instructions, then its 'fixed point processing data rate' is equal
to zero.
'number of bits in a:
Thus:
Fixed point addition instruction' (na)-
Fixed point multiplication instruction' (nimx) Floating point addition instruction' (nar)--- Floating point multiplication instruction' (nimf
The appropriate shortest/single fixed or floating point instruction length which permits full direct addressing of the "main storage".
NB:
1.
When multiple instructions are required to simulate an appropriate single instruction, the number of bits in the above instructions is defined as 16 bits plus the dumber of bits (bax: bimx: biaf bimf) which permits full direct addressing of the "main storage".
16+ biaxi
Diax
16+ birns;
nimx
16+ biafi
Diaf
16+ bimf
nimf
2.
If the addressing capability of an instruction is expanded by using a base register, then the "number of bits in an instruction, fixed or floating point, addition or multiplication' is the number of bits in the instruction with the standard address length including the number of bits necessary to use the base register.
'number of bits in a fixed point operand' (n)
(a) The shortest fixed point operand length; or (b) 16 bit;
whichever is greater.
'number of bits in a floating point operand' (nf)
(a) The shortest floating point operand length; or (b) 30 bit;
whichever is greater.
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